TRANSIENT AND DELAY ANALYSIS FOR ON-CHIP HIGH SPEED VLSI RLCG INTERCONNECTION NETWORK IN 0.18μm TECHNOLOGY

In this paper, the time domain waveform is approximated for calculation of delay, rise, settling time, damping ratio and natural frequency of a second order RLCG on-chip VLSI interconnect line. It can also be evaluated for multiple interconnect systems but due to harmonics higher order systems are ignored. The model is applied to a single RLCG interconnect line which can also be extended for multi-interconnect systems to analyze crosstalk noise. The model evaluates the performance of a system which is expressed in terms of the transient response due to a unit step input. It is easy to generate and evaluate the delay analytically. A closed form expression for the propagation delay of a CMOS gate driving a distributed RLCG line is introduced. On-chip inductance and conductance are expected to have a profound effect on traditional high performance IC design methodologies. In the proposed model, it is shown that when the value of G is increased, the time at which the rise time, settling time and the time when the steady state condition is reached are all increased. So, for high speed circuits one must increase the value of G so that the steady state condition is reached quickly and it is also shown that with the increase in the value of G the delay will reduce. The simulation results performed in SPICE environment justify the efficacy of the proposed model. KeywordsTime Domain Analysis, Damping Ratio, Natural Frequency, Delay Calculation, RLCG Interconnect, VLSI.